In the world of DIY electronics, projects involving programmable logic devices (PLDs) are both challenging and rewarding. These devices offer a great deal of flexibility and versatility for building custom digital circuits. One such component is the XC9572-15PCG84C, a high-performance CPLD (Complex Programmable Logic Device) from Xilinx, which is ideal for medium-scale digital designs. In this article, we will explore a simple yet functional digital clock project using the XC9572-15PCG84C, showcasing how this device can be utilized to create a precise time-keeping circuit.

 

Understanding the XC9572-15PCG84C

The XC9572-15PCG84C is a member of the Xilinx XC9500 series, which are popular CPLDs that provide the user with an easy-to-use platform for creating custom digital logic circuits. This particular model comes in a 84-pin package and is capable of handling complex logic functions. The XC9572 has 72 macrocells, which are flexible, and its speed grade of -15 means it is fast enough for most mid-range applications.

For this project, the XC9572-15PCG84C will serve as the central control unit for the digital clock. We will take advantage of its ability to implement logic functions and control outputs, such as the display and timing signals, while external components will handle tasks like timekeeping and display output.

 

Components Needed

To build the digital clock, you will need the following components:

1. XC9572-15PCG84C CPLD: The brain of the clock, responsible for managing timing and controlling the displays.

2. 4 x 7-segment displays: To show the hours and minutes in a digital format.

3. Crystal Oscillator: To provide a stable clock source for the timing circuit.

4. Button Switches (2): To set the time.

5. Resistors: To limit current to the segments and the switches.

6. Capacitors: To stabilize the oscillator and provide some filtering.

7. Transistors (2): To drive the 7-segment displays.

8. Power Supply: A 5V regulated power supply to power the circuit.

9. PCB or Breadboard: For assembling the circuit.

 

Project Overview

This project involves designing a simple digital clock that can display hours and minutes on 7-segment displays. The XC9572 CPLD will handle the logic required to manage the time and drive the display. We will also incorporate buttons to allow the user to set the clock manually. The clock will run on a 1 Hz signal generated by a crystal oscillator, which will provide accurate timekeeping. The 7-segment displays will show the time in a 24-hour format, with separate displays for hours and minutes.

The primary challenge in this project will be configuring the XC9572-15PCG84C to manage the timing sequence, handle button presses, and control the multiplexed 7-segment display system. The logic design for this project will need to manage multiple aspects, including counting seconds, handling button presses to set the time, and driving the displays to output the time in a readable format.

 

Circuit Design

Crystal Oscillator for Time Base

The first step in building the digital clock is to generate a stable 1 Hz time base, which will be used to count seconds. To do this, we use a crystal oscillator. This oscillator should ideally produce a signal at a frequency of 32.768 kHz, which can be divided down to 1 Hz using a series of binary counters. For simplicity, we'll assume the presence of an external 32.768 kHz crystal oscillator, as it is commonly used in timekeeping circuits.

The 1 Hz signal generated by this oscillator will be fed into the XC9572 CPLD, which will then manage the second count. The CPLD will divide this 1 Hz clock to create a digital time counter.

 

Timekeeping with the CPLD

The XC9572 CPLD will need to manage two main counters: one for the hours and one for the minutes. To keep things simple, we’ll assume a 24-hour format, so the hours counter will count from 0 to 23, while the minutes counter will count from 0 to 59. The CPLD will increment the seconds counter every time a 1 Hz pulse is received. After 60 seconds, it will increment the minutes counter, and after 60 minutes, it will increment the hours counter.

This counter system will be implemented using the macrocells of the CPLD. Each macrocell will store one bit of the counter, and the macrocells will be interconnected to form the full 6-bit minute counter and the 5-bit hour counter. The CPLD will then drive the 7-segment displays based on the values of these counters.

 

Displaying the Time on 7-Segment Displays

We will use four 7-segment displays to show the time. Two displays will show the hours (in the range 00–23), and two displays will show the minutes (in the range 00–59). To drive these displays, the CPLD will need to implement a multiplexing system. Since a 7-segment display has seven segments, each display can represent a digit by turning on the appropriate segments. Each digit from 0 to 9 has a unique combination of segments that need to be lit.

The CPLD will store a lookup table of segment patterns for each digit. For each cycle, the CPLD will quickly switch between the four 7-segment displays, lighting each one for a brief period of time to show the corresponding digit. This process, known as multiplexing, makes it possible to drive multiple displays using fewer I/O pins.

 

Button Presses for Time Setting

To set the time, we will use two buttons: one for adjusting the hours and one for adjusting the minutes. When the user presses the “hour” button, the hours counter will increment by one, and when the “minute” button is pressed, the minutes counter will increment by one. These buttons will be connected to the CPLD inputs, and the CPLD will detect the button presses through simple logic.

Since button presses can be noisy (i.e., they can generate multiple signals due to contact bounce), the CPLD will include debouncing logic to ensure that each button press is registered as a single, clean event. This can be achieved by introducing a small delay or using a shift register to filter out the noise.

 

Programming the CPLD

Now that we have the basic design, the next step is programming the XC9572 CPLD. While the programming process typically involves writing VHDL or Verilog code, for this project, we’ll focus on the general approach to how the CPLD will be configured.

The CPLD will be programmed to do the following:

1. Count the seconds: Every time a 1 Hz pulse is received, increment the seconds counter. When the seconds counter reaches 60, reset it and increment the minutes counter.

2. Count the minutes: Similarly, when the minutes counter reaches 60, reset it and increment the hours counter.

3. Count the hours: The hours counter will count from 00 to 23. When it reaches 24, it will reset to 00.

4. Control the 7-segment displays: The CPLD will use a multiplexing technique to display the current hour and minute on the 7-segment displays. It will cycle through the digits of the hours and minutes, illuminating one display at a time.

5. Handle button presses: When a button is pressed, the CPLD will increment the corresponding counter (hours or minutes).

The logic can be implemented using state machines or counters in the VHDL code. Each state machine will correspond to one of the counters, and transitions will occur based on the clock pulses. The multiplexing logic will also require careful timing to ensure that each display is lit for the correct amount of time.

 

Final Assembly and Testing

Once the circuit is designed and the CPLD is programmed, the next step is to assemble the components on a breadboard or PCB. Ensure that all connections are secure and that the 7-segment displays are connected properly to the CPLD. You will also need to add current-limiting resistors in series with each segment of the display to prevent excessive current from flowing through the LEDs.

After everything is assembled, power up the circuit. The 7-segment displays should show the current time, with the hours and minutes updating every second. Test the button functionality by pressing the buttons to adjust the time.

 

Conclusion

This simple digital clock project demonstrates how to use the XC9572-15PCG84C CPLD to create a functional time-keeping circuit. While the project is relatively straightforward, it provides an excellent opportunity to learn about digital design, logic implementation, and how to use programmable logic devices in real-world applications. By leveraging the power of the XC9572 CPLD, you can create custom digital circuits that are both flexible and efficient, making this project a great starting point for more complex designs.