Details

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BUY 74HC373 https://www.utsource.net/itm/p/901930.html
Octal D-type transparent latch; 3-state

Below is the parameter table and instructions for the 74HC373 D-type transparent latch.

74HC373 Parameter Table

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage	VCC	2.0	5.0	6.0	V
Input Low Voltage	VIL	0.0	0.8	-	V
Input High Voltage	VIH	-	2.0	VCC	V
Output Low Voltage	VOL	0.0	0.1	0.2	V
Output High Voltage	VOH	4.5	4.9	VCC - 0.1	V
Input Leakage Current	IIL	-1.0	-0.4	-0.1	μA
Output Leakage Current	IOL	-1.0	-0.4	-0.1	μA
Propagation Delay Time (Low to High)	tPLH	-	12	25	ns
Propagation Delay Time (High to Low)	tPHL	-	12	25	ns
Power Consumption (per channel)	ICC	-	1.0	10.0	μA

74HC373 Instructions

Overview

The 74HC373 is an octal D-type transparent latch with 3-state outputs. It is used to store data temporarily and can be used in various digital circuits where data needs to be held or transferred.

Pin Configuration

Pin Number	Pin Name	Description
1-7, 14-21	Q0-Q7	Latched Output (3-state)
8	GND	Ground
9	LE	Latch Enable (active low)
10-16, 22-29	D0-D7	Data Input
17	OE	Output Enable (active low)
18	VCC	Positive Supply Voltage

Operation

1. Data Latching:

   • When the Latch Enable (LE) input is high, the outputs Q0-Q7 follow the inputs D0-D7.
   • When LE is low, the outputs Q0-Q7 hold the last state of the inputs D0-D7.

2. Output Enable:

   • When the Output Enable (OE) input is high, the outputs Q0-Q7 are in a high-impedance state (tristate).
   • When OE is low, the outputs Q0-Q7 are active and can drive the connected circuitry.

3. Power Supply:

   • Connect V_CC to the positive supply voltage (2.0V to 6.0V).
   • Connect GND to the ground.

4. Input and Output Levels:

   • Ensure that the input voltages (D0-D7) are within the valid range (V_IL to V_IH).
   • The output voltages (Q0-Q7) will be either close to V_CC or close to GND when OE is low.

Example Application

• Data Bus Buffering:

  • Use the 74HC373 to buffer data on a bus. Connect the data lines to the D inputs, and use the LE and OE pins to control when the data is latched and when the outputs are active.

• Memory Address Latching:

  • Use the 74HC373 to latch address lines in a memory system. Connect the address lines to the D inputs, and use the LE pin to latch the address when needed.

Notes

• Ensure that the power supply voltage is stable and within the specified range to avoid damage to the device.
• Proper decoupling capacitors should be used near the V_CC and GND pins to reduce noise and improve stability.

This table and instructions should provide a comprehensive overview of the 74HC373 D-type transparent latch.

(For reference only)