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BUY AT28C64B-15JC https://www.utsource.net/itm/p/1401457.html
64K 8K x 8 CMOS E2PROM with Page Write and Software Data Protection
Parameter | Symbol | Min | Typical | Max | Unit | Notes |
---|---|---|---|---|---|---|
Supply Voltage | VCC | 4.5 | - | 5.5 | V | Operating voltage range |
Standby Current | ICC(standby) | - | 10 | - | μA | With /OE and /WE high |
Active Current (Read) | ICC(read) | - | 30 | - | mA | At VCC = 5V, fCLK = 50 MHz |
Active Current (Write) | ICC(write) | - | 40 | - | mA | At VCC = 5V, fCLK = 50 MHz |
Access Time | tAA | - | 70 | 150 | ns | Access time from address valid to data valid |
Write Cycle Time | tWC | - | 550 | 700 | μs | Time required for a complete write cycle |
Address Latch Time | tALH | - | 20 | 40 | ns | Time from /OE low to address valid |
Output Hold Time | tOHZ | - | 10 | 20 | ns | Time data is held after /OE goes high |
Output Disable Time | tDS | - | 10 | 20 | ns | Time from /OE high to output disabled |
Write Enable Pulse Width | tWP | - | 100 | 200 | ns | Minimum pulse width for /WE |
Write Recovery Time | tWR | - | 10 | 20 | ns | Time from /WE high to next operation |
Data Setup Time | tDSU | - | 10 | 20 | ns | Time data must be stable before /WE low |
Data Hold Time | tDH | - | 0 | 10 | ns | Time data must be stable after /WE low |
Address Setup Time | tAS | - | 10 | 20 | ns | Time address must be stable before /OE or /WE low |
Address Hold Time | tAH | - | 0 | 10 | ns | Time address must be stable after /OE or /WE low |
Power-down Time | tPD | - | 0 | 10 | μs | Time to enter power-down mode |
Power-up Time | tPU | - | 0 | 10 | μs | Time to exit power-down mode |
Instructions:
Power Supply:
- Ensure the supply voltage (VCC) is within the specified range (4.5V to 5.5V).
Addressing:
- Provide the correct address lines (A0-A12) to select the desired memory location.
- Address setup time (tAS) and hold time (tAH) must be respected to ensure reliable data access.
Data Read:
- Set the output enable (/OE) low to read data from the selected address.
- Data will be available on the data lines (D0-D7) after the access time (tAA).
- Ensure the output hold time (tOHZ) is respected before disabling the output by setting /OE high.
Data Write:
- Set the write enable (/WE) low to initiate a write cycle.
- Ensure the data setup time (tDSU) and data hold time (tDH) are respected.
- The write cycle time (tWC) must be observed to ensure the data is written correctly.
- After writing, ensure the write recovery time (tWR) is respected before initiating another operation.
Power Management:
- To enter power-down mode, set both /OE and /WE high.
- To exit power-down mode, bring either /OE or /WE low.
- Observe the power-down time (tPD) and power-up time (tPU) to ensure proper operation.
Current Consumption:
- Monitor the active current (ICC(read/write)) during read and write operations to avoid exceeding the maximum ratings.
- Standby current (ICC(standby)) should be considered when the device is not in use.
Timing Diagrams:
- Refer to the timing diagrams provided in the datasheet for more detailed information on signal interactions and timing requirements.
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