Details
BUY AD7401YRWZ https://www.utsource.net/itm/p/12377457.html
Parameter | Symbol | Conditions | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
Supply Voltage | VDD | 2.7 | 5.5 | V | ||
Supply Current | IDD | 300 | μA | |||
Differential Input Range | VIN+ - VIN- | -0.3 | 1.6 | V | ||
Common Mode Input Range | VCM | -0.3 | 1.8 | V | ||
Output Voltage Swing | VOUT | RL = 10 kΩ to VDD | 0.02 | VDD-0.02 | V | |
Bandwidth | BW | Small Signal, G=1 | 200 | kHz | ||
Slew Rate | SR | 0.4 | V/μs | |||
CMRR | f = 1 kHz | 90 | dB | |||
PSRR | f = 1 kHz | 80 | dB | |||
Input Bias Current | IB | ±1 | ±1 | nA | ||
Input Offset Voltage | VOS | Initial | -2 | 2 | mV | |
Gain Error | G = 1 | -0.5 | 0.5 | % |
Instructions for Use:
Power Supply:
- Ensure the supply voltage (VDD) is within the range of 2.7V to 5.5V.
- Connect a bypass capacitor (typically 0.1μF) close to the power pins to minimize noise.
Input Signals:
- Keep differential input signals within the range of -0.3V to 1.6V relative to each other.
- Maintain common mode input voltages between -0.3V and 1.8V relative to ground.
Output Configuration:
- The output can swing from 0.02V above ground to 0.02V below VDD with a 10kΩ load.
- For optimal performance, ensure the output load does not exceed the specified limits.
Operational Considerations:
- For best performance in terms of bandwidth and slew rate, operate within recommended conditions.
- Be aware of the common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) when designing circuits sensitive to these parameters.
Biasing and Offset:
- Account for the input bias current and input offset voltage in your circuit design to avoid unexpected behavior or inaccuracies.
Gain Settings:
- Adjust gain settings as needed, ensuring gain error remains within acceptable limits for your application.
Note: Always refer to the specific datasheet provided by Analog Devices for the most accurate and detailed information about the AD7401YRWZ.
(For reference only)View more about AD7401YRWZ on main site