Details

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BUY 74LVC109D,112 https://www.utsource.net/itm/p/12594137.html

Parameter	74LVC109D	74LVC112
Description	Hex D-Type Flip-Flop with Clear	Dual J-K Flip-Flop with Clear
Function	Stores data and changes state on clock edge	Stores data and changes state based on J and K inputs
Supply Voltage (VCC)	1.65V to 3.6V	1.65V to 3.6V
Input Voltage (VIH)	Min: 2.0V, Max: VCC	Min: 2.0V, Max: VCC
Input Voltage (VIL)	Max: 0.8V	Max: 0.8V
Output Voltage (VOH)	Min: VCC - 0.1V	Min: VCC - 0.1V
Output Voltage (VOL)	Max: 0.1V	Max: 0.1V
Propagation Delay	Typically 3.5ns at VCC = 3.3V	Typically 4.5ns at VCC = 3.3V
Power Dissipation	Low power CMOS technology	Low power CMOS technology
Operating Temperature	-40°C to +85°C	-40°C to +85°C
Package	Various including SOIC, TSSOP	Various including SOIC, TSSOP

Instructions for Use:

74LVC109D:

1. Connect Power Supply: Connect VCC to the appropriate voltage level (1.65V to 3.6V) and GND to ground.
2. Data Input (D): Apply the data signal you wish to store.
3. Clock Input (CLK): The flip-flop captures the data on the rising edge of the clock signal.
4. Clear Input (CLR): Active-low clear input resets the flip-flop output to 0 when pulled low.
5. Output (Q and Q?): Provides the stored data and its complement.

74LVC112:

1. Connect Power Supply: Connect VCC to the appropriate voltage level (1.65V to 3.6V) and GND to ground.
2. J and K Inputs: Apply the J and K signals which determine the next state of the flip-flop.
3. Clock Input (CLK): The flip-flop updates its state on the rising edge of the clock signal based on J and K inputs.
4. Clear Input (CLR): Active-low clear input resets the flip-flop outputs to 0 when pulled low.
5. Outputs (Q and Q?): Provides the current state of the flip-flop and its complement.

Ensure all connections are secure and within specified voltage levels to avoid damage to the device.

(For reference only)