Details

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BUY CD4071BD https://www.utsource.net/itm/p/402293.html
CMOS OR GATES

Parameter	Symbol	Conditions	Min	Typ	Max	Unit
Supply Voltage	VDD		3		18	V
Input Low Voltage	VIL	IL = 1 mA			1.5	V
Input High Voltage	VIH	IH = -10 μA	3.5			V
Output Low Voltage	VOL	IOL = 4 mA			0.4	V
Output High Voltage	VOH	IOH = -0.4 mA	2.4			V
Propagation Delay Time	tpLH, tpHL	VDD = 15V, VOH = 3V, VOL = 0.8V		27		ns
Power Dissipation	PD	Continuous			100	mW

Instructions for Use:

1. Supply Voltage (V_DD):

   • Ensure the supply voltage is within the specified range of 3V to 18V to avoid damage to the device.

2. Input Signals:

   • For reliable operation, input voltages should be kept below 1.5V for logic low and above 3.5V for logic high when operating at the maximum supply voltage.

3. Output Signals:

   • The output can drive up to 4mA in low state and sink up to 0.4mA in high state while maintaining the specified voltage levels.

4. Propagation Delay:

   • The typical propagation delay time is 27ns under standard conditions (V_DD = 15V).

5. Power Dissipation:

   • Do not exceed 100mW continuous power dissipation to prevent overheating.

6. Handling Precautions:

   • Handle with care as static electricity can damage the component. Use appropriate ESD protection measures.

7. Mounting:

   • Ensure proper mounting on a PCB with adequate heat sinking if necessary, especially under high load conditions.

(For reference only)