Details

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BUY MP1517DR-LF-Z https://www.utsource.net/itm/p/4897818.html
IC REG MULTI CONFG ADJ 4A 16QFN

Parameter	Symbol	Test Conditions	Min	Typ	Max	Unit
Input Voltage	VIN	-	2.7	-	5.5	V
Output Voltage	VOUT	Set by external resistors	-	-	-	V
Switching Frequency	fSW	-	-	1.0	-	MHz
Quiescent Current	IQ	VIN = 3.6V, no load	-	80	-	μA
Shutdown Current	ISD	VIN = 3.6V, SHDN = 0V	-	0.1	-	μA
Load Regulation	ΔVOUT	IOUT from 0 to 300mA	-	±1	-	%
Line Regulation	ΔVOUT	VIN from 2.7V to 5.5V	-	±1	-	%
Dropout Voltage	VDROPOUT	IOUT = 300mA	-	300	-	mV

Instructions for MP1517DR-LF-Z

1. Input Capacitor Selection:

   • Use a ceramic capacitor with X5R or X7R dielectric.
   • Recommended value: 1μF to 10μF.

2. Output Capacitor Selection:

   • Use a ceramic capacitor with X5R or X7R dielectric.
   • For stability, a minimum of 1μF is recommended.

3. Setting Output Voltage:

   • The output voltage can be set using two external resistors (R1 and R2) connected between the FB pin, VOUT, and GND.
   • Use the formula ( V_ = V_ times (1 + frac) ), where ( V_ = 0.8V ).

4. Shutdown Function:

   • Apply a logic low signal (< 0.4V) to the SHDN pin to put the device into shutdown mode.
   • A logic high signal (> 1.2V) on the SHDN pin enables normal operation.

5. Thermal Considerations:

   • Ensure adequate heat dissipation if operating at higher currents or in high ambient temperatures.
   • Use a PCB layout that provides good thermal conductivity.

6. PCB Layout Guidelines:

   • Keep input and output capacitors close to the IC.
   • Ensure wide and short traces for power paths.
   • Place the feedback resistors near the FB pin to minimize noise pickup.

7. Handling Precautions:

   • This device is sensitive to electrostatic discharge (ESD).
   • Follow proper ESD handling procedures during assembly and testing.

(For reference only)